The present disclosure relates generally to the fabrication of semiconductor devices and, more particularly, to a method and process for forming a gate stack structure with an extra thin oxide layer.
Semiconductor device geometries have dramatically decreased in size since such devices were first introduced several decades ago. Since then, integrated circuits have generally followed the two year/half-size rule (often called Moore""s Law), which means that the number of devices on a chip doubles every two years. Today""s fabrication plants are routinely producing devices having 0.35 .mu.m and even 90 nm feature sizes.
Presently, there is a great demand for shrinking semiconductor devices to provide an increased density of devices on the semiconductor chip that are faster and consume less power. The scaling of devices in the lateral dimension requires vertical scaling as well so as to achieve adequate device performance. This vertical scaling requires the effective electrical thickness of the gate dielectric to be reduced so as to provide the required device performance. Silicon dioxide has been the preferred gate dielectric material. However, newer technologies are requiring effective thicknesses of the silicon dioxide below currently believed limits (e.g.,  less than 10 Angstroms). Further, for deep sub-micron CMOS devices and circuits, gate dielectrics have been scaled down aggressively toward direct tunneling region. For ultra-thin SiO2, leakage current will increase tremendously as thickness is reduced. This will cause large standby power consumption, thus making products commercially not acceptable.
For the application of smaller CMOS devices such as 0.065 um devices, SiO2 is not a feasible choice for the gate dielectric, and a new gate dielectric must be created with thin dielectric thickness, low leakage current density and high driving capability.
In addition, even with new gate dielectric materials, the increasing problems of excessive gate leakage current in ultra thin oxide and the dopant impurity penetration have becoming the major obstacles for the continuing downscaling of CMOS technology. Different nitridation methods have been proposed to replace pure SiO2 because of leakage current and effective oxide thickness reduction ability. For example, ultra thin nitride/oxide(N/O) stack gate dielectric and Decouple Plasma Nitrogen (DPN) have been proposed as viable alternatives to silicon dioxide for 0.1 um device because of their good impurity diffusion barrier property and low gate leakage current density. However, it is difficult to shrink the dielectric thickness in N/O stack gate or nitrided oxide. Although, it is theoretically possible to shrink the dielectric thickness in N/O stack gate or nitrided oxide and reduce the gate leakage current density, the drain current will be deteriorated. Moreover, plasma direct treatment on gate dielectric can easily induce the oxide damage and then reduce the carrier mobility and driving current.
What is needed is a new process to form a gate stack structure with thin oxide and with low leakage current.
The present disclosure provides a method for forming a gate stack structure for semiconductor devices requiring a thin dielectric layer. The disclosed method comprises steps such as forming a dielectric layer on a substrate; applying a plasma nitridation process on the formed dielectric layer; applying a first anneal process on the deposited dielectric layer; etching the dielectric layer to a predetermined thickness; applying a second anneal process using an oxygen environment on the etched dielectric layer after the etching; and forming a gate electrode layer on top of the dielectric layer. The etching makes the top portion of the etched dielectric layer have a significantly higher concentration of nitrogen than the lower portion of the etched dielectric layer so as the leakage current is significantly reduced.
In one example, a novel gate stack manufacturing process is provided to gain a low leakage current density, high drain current and less boron penetration performance by combining decouple plasma nitridation treatment, post nitridation anneal, and diluate etchant etch back process. Another benefit is that there is no complicated nitridation process introduced. The etch back process is fully compatible with the current CMOS process flow and does not require any new equipment or new process design.